Data entry terminal having data correction means

ABSTRACT

A data entry terminal is disclosed for use in a data communication system. The terminal includes a content addressable memory for storing a variable character length data field and an associated field separator. A message comprised of at least one data field and a separator is outputted from the memory in a character series sequence in the order in which the characters were entered into the memory. The length of the message may be shortened by deleting the data characters in the last entered data field.

United States Patent [191 Klosky et al.

1 DATA ENTRY TERMINAL HAVING DATA CORRECTION MEANS [75] Inventors: JohnPatrick Klosky, Mentor; James Lucian Maynard, Northfield, both of Ohio[73] Assignee: Addressograph Multigraph Corporation, Cleveland, Ohio 22Filed: June 26, 1973 21 App1.No.:373,777

[52] US. Cl. 340/1725 [51] Int. Cl. G061 l/00; G06f 13/00 [58] Field ofSearch 340/1725, 324 A [56] References Cited UNITED STATES PATENTS2,911,624 11/1959 Booth 340/174 3,456,243 7/1969 Cass 340/1725 3,465,2999/1969 Schellenberg.... 340/1725 3,501,746 3/1970 Vosbury 340/17253,518,629 6/1970 Frankel 340/1725 3,544,975 12/1970 Hunter 340/1725IMPR/IW" COVTROL [4 1 Sept. 9, 1975 3,636,519 1/1972 Heath 340/17253,643,252 2/1972 Roberts. 340/324 A 3,651,481 3/1972 Evans... 340/17253,683,359 8/1972 Kleinschanitz. 340/324 A 3,699,531 10/1972 Heimann340/1725 Primary ExaminerGareth D. Shaw Assistant Examiner-James D.Thomas Attorney, Agent, or FirmRobert B. Sundheim; Harry M. Fleck, Jr.

[5 7] ABSTRACT A data entry terminal is disclosed for use in a datacommunication system. The terminal includes a content addressable memoryfor storing a variable character length data field and an associatedfield separator. A message comprised of at least one data field and aseparator is outputted from the memory in a character series sequence inthe order in which the characters were entered into the memory. Thelength of the message may be shortened by deleting the data charactersin the last entered data field.

14 Claims, 39 Drawing Figures PATENTEBSEP 91915 1805,02?

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1. A data entry terminal comprising: content addressable memory meansfor storing a variable length message comprised of data charactersentered therein and including at least one variable character lengthdata field and a field separator; data entry means for entering a saidmessage into said memory means so that said message includes at leastone said variable character length data field and a said fieldseparator; means for outputting a said message from said memory means insuch a manner that the data characters are outputted in a seriessequence in the order in which they were entered into said memory meansand such that a said field separator precedes the first enteredcharacter in an associated variable character length data field; meansfor re-entering a said outputted message into said memory means andincluding controllable gating means for passing data characters to bere-entered into said memory means in a said series sequence; messagemodifying means for deleting from a said outputted message the datacharacters in the last entered data field in repsonse to a clear commandsignal and including gate control means for controlling saidcontrollable gating means to prevent re-entry of the last enteredcharacter in the last entered data field each time a said outputtedmessage is re-entered into said memory means and independently of thecharacter length of said data field until all of said data characters insaid data field have been deleted from said message.
 2. A data entryterminal as set forth in claim 1 wherein said terminal includes circuitmeans defining a series transmission path with said outputting means andsaid re-entering means, said transmission path normally having a firstcharacter length for storing at any one point in time a fixed number ofsaid outputted data characters, said message modifying means includingmeans for selectively shortening the length of said transmission path byat least one character length.
 3. A data entry terminal as set forth inclaim 2, wherein said data transmission path includes a plurality ofcharacter storage registers connected in series for sequentially storingsaid outputted data characters, a plurality of said controllable gatingmeans each being interposed between two successive character storageregisters, said gate control means including means for controllingselected ones of said controllable gating means to prevent a datacharacter in a first of said registers from being transferred to asecond of said registers through a said controllable gating means.
 4. Adata entry terminal as set forth in claim 3, including registerbypassing means for connecting the output of one of said registers withthe input of another of said registers while bypassing an intermediateone of said registers so that data stored in said one register istransferred to said second register while bypassing said intermediateregister.
 5. A terminal as set forth in claim 4, whereIn said bypassingcircuit means includes a normally disabled data entry gating means andwherein said gate control means includes means for selectively enablinga said normally disabled gating means for passing the said datacharacter in said one register to said another register.
 6. A data entryterminal as set forth in claim 2, wherein said data transmission pathincludes a plurality of shift registers for sequentially storing a likeplurality of said outputted data characters in said series sequence withsaid registers being interposed between said outputting means and saidre-entering means, at least one controllable intermediate gating meansinterposed between successive ones of said plurality of shift registersfor normally passing a data character from the immediately precedingshift register into the immediately succeeding shift register; registerbypassing circuit means for bypassing at least one of said shiftregisters and including gating means for connecting the output of apreceding shift register means with the input of a succeeding shiftregister means while bypassing at least one intermediate shift registermeans; said gate control means including circuit means for controllingsaid plurality of intermediate gating means and said bypass circuitgating means for effectively varying the length of said datatransmission path.
 7. A data entry terminal as set forth in claim 6,including a second register bypass path, said gate control meansincluding means for selectively controlling said gating means in each ofsaid register bypassing circuits.
 8. A data entry terminal as set forthin claim 7, including circuit means for connecting the second registerbypassing circuit means with the output of a said shift registerbypassed by said first register bypassing circuit means.
 9. A data entryterminal as set forth in claim 2, wherein said transmission pathinterconnects said outputting means and said re-entering means to definea recirculating path between the input of said memory means and theoutput thereof to thereby define a recirculating memory means, saidrecirculating memory means being comprised of static shift registers forsequentially shifting said characters in said series sequence fromregister to register in synchronism with shift pulses applied to saidregisters.
 10. A data entry terminal as set forth in claim 9, whereinsaid recirculating memory means is comprised of a plurality of bitserial shift register means for shifting said data characters in saidseries sequence, each said data character being comprised of a pluralityof bits with the bits of each charcter being shifted in series sequencewith the most significant bit being shifted first.
 11. A data entryterminal comprising; content addressable memory means for storing avariable length message comprised of data characters entered therein andincluding at least one variable character length data field and a fieldseparator; data entry means for entering a said message into said memorymeans so that said message includes at least one said variable characterlength data field and a said field separator; means for outputting asaid message from said memory means in such a manner that the datacharacters are outputted in a series sequence in the order in which theywere entered into said memory means and such that a said field separatorprecedes the first entered character in an associated variable characterlength data field; means for re-entering a said outputted message intosaid memory means and including controllable gating means for passingdata characters to be re-entered into said memory means in a said seriessequence; message modifying means for deleting from a said outputtedmessage the data characters in the last entered data field in responseto a clear command signal and including gate control means forselectively controlling said re-entry gating means to prevent re-entryof the last entered character in the last entered data field Each time asaid outputted message is re-entered into said memory means andindependently of the character length of said data field until all ofsaid data characters in said data field have been deleted from saidmessage; said terminal includes circuit means defining a seriestransmission path with said outputting means and said re-entering means,said transmission path normally having a first character length forstoring at any one point in time a fixed number of said outputted datacharacters, said message modifying means including means for selectivelyshortening the length of said transmission path by at least onecharacter length, said transmission path interconnects said outputtingmeans and said re-entering means to define a recirculating path betweenthe input of said memory means and the output thereof to thereby definea recirculating memory means, said recirculating memory means beingcomprised of static shift registers for sequentially shifting saidcharacters in said series sequence from register to register insynchronism with shift pulses applied to said registers, decoding meansfor decoding specific data characters shifted through a specific one ofsaid registers, said specific data characters being respectivelyrepresentative of an end of message indicator and a said clear command,each said indicator and each said command being defined by at least onecoded multibit data character, said decoding means providing an outputclear command signal in response to decoding a said clear command and asaid end of message signal in response to decoding a said end of messageindicator, said message modifying means including circuit meansresponsive to a said clear command signal for instituting operation toclear the data characters from the last entered data field and itsassociated field definer, and circuit means responsive to a said end ofmessage signal indicative that said clearing operation has beencompleted.
 12. A data entry terminal as set forth in claim 11, whereinsaid circuit means responsive to a said end of message signal includescircuit means deleting said clear command from said message.
 13. A dataentry terminal as set forth in claim 11, wherein said terminal includescircuit means for automatically entering a said end of message indicatorinto said memory means after each data character is entered into saidmemory means and circuit means for entering data characters into saidmemory means so as to effectively be written over the end of messageindicator entered after the preceding data characters.
 14. A data entryterminal comprising: content addressable memory means for storing avariable length message comprised of data characters entered therein andincluding at least one variable character length data field and a fieldseparator; data entry means for entering a said message into said memorymeans so that said message includes at least one said variable characterlength data field and a said field separator; means for outputting asaid message from said memory means in such a manner that the datacharacters are ouputted in a series sequence in the order in which theywere entered into said memory means and such that a said field separatorprecedes the first entered character in an associated variable characterlength data field; means for re-entering a said outputted message intosaid memory means and including controllable means for passing datacharacters to be re-entered into said memory means in a said seriessequence; message modifying means for deleting from a said outputtedmessage the data characters in the last entered data field in responseto a clear command signal and including control means for selectivelycontrolling said reentry means to prevent re-entry of the last enteredcharacter in the last entered data field each time a said outputtedmessage is re-entered into said memory means and independently of thecharacter length of said data field until all of said data characters insaid data fiEld have been deleted from said message, said data entrymeans including means for entering a clear command into said memorymeans wherein said clear command includes at least one multibitcharacter, and decoding means for decoding said outputted data for thepresence of a said clear command and providing a said clear commandsignal in accordance therewith.